A first example of a conventional phase locked loop for transmission of signals is illustrated in FIG. 1. This phase locked loop has a phase-frequency detector 1 (PFD), a charge pump 2 (CP), a loop filter 3 (LF), a voltage controlled oscillator 4 (VCO), a programmable divider 5, a pulse shaping circuit 6 (PSC), and a sigma delta circuit 7 (ΔΣ). The phase-frequency detector 1 detects the phase difference between two input signals, REF and OSC, and generates output pulses depending on the phase difference. The charge pump 2 outputs electric current according to the output signal from the phase-frequency detector 1. The loop filter 3 attenuates the output signal from the charge pump 2. In the voltage-controlled oscillator 4, output voltage Vctrl1 of the loop filter 3 is supplied to a first control terminal to control the frequency. The programmable divider 5 divides output signal fout from the voltage-controlled oscillator 4 and feeds it back to the phase-frequency detector 1. The pulse shaping circuit 6 transforms an incoming transmission pulse train TX_DATA into a prescribed transmission waveform voltage Vctrl2 and sends it to a second control terminal of the voltage-controlled oscillator 4. The sigma delta circuit 7 carries out sigma delta modulation of a constant CS representing a transmitting channel, namely a carrier frequency and outputs a frequency division number set signal for the programmable divider 5. (See Non-Patent Document 1, Seong Hwan Cho et al, “A 6.5 GHz CMOS FSK Modulator for Wireless Sensor Applications,” Symposium on VLSI Digest of Technical Papers, pp. 182–185, 2002.)
Next, an explanation is given of the first conventional phase locked loop. The phase-frequency detector 1, charge pump 2, loop filter 3, voltage controlled oscillator 4, programmable divider 5, and sigma delta circuit 7 constitute a fractional-N phase locked loop. When a constant value CS which is more than N and less than N+1 is entered, the sigma delta circuit 7 outputs N or N+1 randomly in a way that the average of output signals is equal to CS. As a result, the average division number for the programmable divider 5 is a fractional number between N and N+1, namely constant CS and thus a fractional-N phase locked loop is realized. This type of fractional-N phase locked loop is described, for example, in Non-patent Document 2, Razavi, “RF Microelectronics,” 1998, Prentice Hall, pp. 279–283.
Next, an explanation is given of the pulse shaping circuit 6. The pulse shaping circuit 6 shapes an incoming binary pulse train as transmission pulse train TX_DATA, into a prescribed transmission waveform and supplies transmission waveform voltage Vctrl2 to the second control terminal of the voltage controlled oscillator 4. For example, the pulse shaping circuit 6 comprises a Gaussian filter and a digital/analog (D/A) converter in order to perform GFSK (Gaussian Filtered Frequency Shift Keying), which reduces the required frequency bandwidth by a Gaussian low-pass filter.
In the first conventional phase locked loop, the transfer function for transfer from transmission waveform voltage Vctrl2 to output signal fout from the voltage-controlled oscillator 4 is a high-pass transfer function. In other words, in the phase locked loop, the loop band is wide and the symbol frequency is in a high-pass filter's blocking or transitional band, the incoming modulated signal with transmission waveform voltage Vctrl2 degrades when outputted as signal fout.
Since the loop bandwidth of the phase locked loop varies depending on the temperature or device, the rate of degradation varies accordingly. A possible approach to avoiding this may be to lower the loop band and set the symbol frequency to the passband of the high pass filter. However, this approach has a drawback that the convergence time for the phase locked loop increases and, therefore, the time to activate the phase locked loop cannot be satisfied. Therefore, in order to satisfy both convergence time and transmission requirements, the first conventional phase locked loop adopts a loop bandwidth switch method in which, for convergence the loop bandwidth is widened and, for transmission the charge pump current for the charge pump CP and the time constant for the loop filter LF are changed by the signal band to narrow the loop bandwidth.
FIG. 3 shows a second example of a conventional phase locked loop. This phase locked loop comprises a phase-frequency detector 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator 4, a programmable divider 5, a Gaussian filter 8, a sigma delta circuit 7, and a digital filter 10 (DF). The Gaussian filter transforms transmission pulse train TX_DATA into a GMSK signal. The sigma delta circuit 7 is connected with an adder 9 which adds a frequency division number set signal to the output of the Gaussian filter 8. The digital filter 10 has a characteristic opposite to the loop characteristic of the phase locked loop. (See Non-patent Document 3, Michael H. Perrott et al, “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE JSSC Vol. 32, No.12, pp.2048–2060, December 2002.)
The second conventional phase locked loop works as follows. When the phase locked loop is in a steady state, the central frequency of the voltage controlled oscillator 4 is the product of a constant CS specifying the frequency division number and the frequency fref of reference signal REF, namely CS×fref. In transmission, transmission pulse train TX_DATA enters the Gaussian filter (GF) 8 where its waveform is shaped; then it is transformed by the digital filter 10 into a signal whose degradation caused by the loop characteristic of the phase locked loop is corrected. The output from the digital filter 10 is added to the signal CS representing the carrier frequency before being introduced into the sigma delta circuit 7. The output from the sigma delta circuit 7 enters the programmable divider 7 where the frequency division number is updated.
To explain simply, let's assume that the digital filter 10 does not exist and the output of the Gaussian filter is connected with the output of the sigma delta circuit 7. It is also assumed that the frequency of transmission pulse train TX_DATA is far higher than the loop band of the phase locked loop (for example, ten times higher).
The output signal from the sigma delta circuit 7 is a signal which digitally represents a transmission-modulated signal. As this signal enters the programmable divider 5, the phase of the output signal from the programmable divider 5 changes. This phase change is conveyed to the output of the voltage controlled oscillator 4 through the phase-frequency detector 1, charge pump 2, and loop filter 3, generating a modulated signal with a central frequency of CS×fref. The transfer function which is used for the output signal form the sigma delta circuit 7 to be transferred to the output of the voltage controlled oscillator 4 is a low-pass function. Therefore, the output signal from the voltage controlled oscillator 4 is a signal which is obtained by multiplying the output signal from the sigma delta circuit 7 by the low pass transfer function of the phase locked loop.
It would be possible to output a modulated signal without the digital filter 10. However, since there is attenuation in the modulated waveform due to the low pass characteristic of the phase locked loop, there would be operational difficulty in case that the frequency of transmission pulse train TX_DATA is sufficiently high for the loop bandwidth of the phase locked loop. In the second conventional phase locked loop, the digital filter 10 is provided in order to prevent attenuation in the modulated waveform. The characteristic of the digital filter 10 is opposite to the low pass characteristic of the phase locked loop so that the transmission signal is amplified taking into consideration its degradation which would be caused by the low pass characteristic of the phase locked loop, before being introduced into the programmable divider 5. This amplification makes it possible to achieve a higher symbol rate regardless of the loop bandwidth.
The problem of the first conventional phase locked loop is explained below referring to FIG. 2. In the graph of FIG. 2, the vertical axis represents frequency f and the horizontal axis represents time t. fc represents carrier frequency, Δf modulation frequency, and ts modulation start time. If digital transmission signals are, for example, “11111111,” the ideal modulated waveform should be like the one as expressed by solid line A, namely a waveform which is Δf away from carrier frequency fc. However, if the loop bandwidth is larger than the packet length, the modulated waveform would degrade like the one as expressed by alternate long and short dash line B. Therefore, the loop band of the phase locked loop should be low enough not to cause signal degradation even when the maximum packet length of transmission symbol is sent.
On the other hand, in the voltage controlled oscillator 4 as a component of the phase locked loop, a frequency drift as expressed by alternate long and two short dashes line C (FIG. 2) occurs. In order for the phase locked loop to compensate for this drift, the loop bandwidth should be wide enough to follow the frequency drift of the voltage-controlled oscillator 4 which occurs within a packet.
When the first conventional phase locked loop is used in an application that digital signals representing a succession of “1” (for example, “11111111”) are transmitted, coexistence of the transmission characteristic and drift compensation characteristic would be difficult and thus another means to reduce drift of the voltage controlled oscillator 4 is needed.
In the second conventional phase locked loop, a high clock rate is needed because the sigma delta circuit 7 and the digital filter 10 require highly modulated waveform accuracy. This means that frequency fref of reference signal REF mush be high and the digital circuit, including the phase-frequency detector 1, the sigma delta circuit 7, and the digital filter 10, must operate at high speed. This raises problems related to operating limit frequencies and power consumption.
In short, in the first conventional phase locked loop, when signals representing a succession of “1” (for example, “11111111”) are transmitted, modulated signal degradation occurs as the phase locked loop locks in; and in the second conventional phase locked loop, since, in order to reduce transmission signal errors, it must operate at a sampling frequency which is sufficiently high for the symbol rate, fref must be set high for the symbol rate, and therefore, the digital circuit including the phase-frequency detector might have trouble in operation.